- A high-aperture EUV lithography equipment weighs as much as two Airbus A320s and incorporates more than 100,000 parts
- The first integrated circuits manufactured with this machine will come out of node 14A during 2026
ASML is currently preparing to ship its second extreme ultraviolet (UVE) and high aperture (High-NA) lithography equipment to one of its customers. We still do not know its identity, but what we do know is that for now the only semiconductor manufacturer that already has one of these very complex and very expensive machines installed in one of its plants is Intel. In fact, it is in the testing phase at its Hillsboro (USA) factory.
Just a few hours ago we participated in a technical session led by the Intel engineers who are operating this machine and they told us very interesting things. However, before we get into trouble, it is worth briefly reviewing what we have at hand in this article. A high-aperture EUV lithography equipment like the one Intel has in Hillsboro weighs as much as two Airbus A320s and incorporates more than 100,000 parts, 3,000 cables, 40,000 bolts, and also more than 2 km of electrical connections.
Each of them costs 350 million euros and ASML engineers have invested a decade in developing the technology necessary to develop this machine, which, in reality, is a second-hand extreme ultraviolet (EUV) lithography equipment. generation. One more interesting note: ASML sent Intel this equipment, whose commercial name is TWINSCAN EXE:5000, packaged in more than 250 boxes that were deposited inside 43 cargo containers. They flew to Seattle on several cargo planes, and from there they moved them to their final location in Oregon using 20 trucks. Quite an odyssey.
Intel has a very ambitious plan to take advantage of high-aperture SVU machines
Currently, Intel engineers are engaged in the calibration process of the first high-aperture UVE equipment that has passed through their hands. Presumably in the coming months this American company will buy more machines of this type from ASML because, as we can guess, just one will not be at all sufficient to satisfy its manufacturing needs for very highly integrated semiconductors. In fact, ASML plans to deliver about 20 devices of this type to its customers annually starting in 2025.
To develop the high-aperture UVE lithography equipment, ASML engineers have developed a very advanced optical architecture that has an aperture of 0.55 compared to the value of 0.33 found in first-generation UVE lithography equipment. This refinement of optics allows higher resolution patterns to be transferred to the wafer, making it possible to manufacture chips using more advanced integration technologies than those currently used in 3nm nodes.
In the article we dedicated to the Rayleigh criterion we explained in great detail what the ‘NA’ (numerical aperture) parameter consists of, but in this text for now it is enough for us to know that this variable identifies the aperture value of the optics used by the team. lithographic. In this context, this parameter essentially reflects the same thing as the aperture value when we talk about the optics of a camera, so it determines the amount of light that the optical elements are capable of collecting. As we can guess, the more light they collect, the better.
However, this is not all. ASML has also improved the mechanical systems responsible for wafer handling to make it possible for a single high-aperture UVE machine to be capable of producing more than 200 wafers per hour. The cover photograph of this article allows us to sense the extreme complexity and sophistication of one of these devices, which, by the way, would not be possible without the cooperation of other companies, such as the German ZEISS or Cymer, a company of American origin. which is currently well established within the ASML structure.
In 2025, Intel will begin conducting the first product tests using high-aperture EUV lithography equipment.
The slide that we publish below these lines describes the itinerary that Intel has set until 2027 and contains something very interesting: in 2025 it will begin to carry out the first product tests using the high-aperture UVE lithography equipment. The first integrated circuits manufactured with this machine will come out of node 14A during 2026, and in 2027 Intel will launch a presumably improved revision of this node that will be named 14A-E. These two nodes will mark the start of chip manufacturing using ASML’s new UVE and high aperture lithography equipment.
According to Intel, high-aperture UVE lithography equipment will help integrated circuit manufacturers who opt for them to sustain Moore’s law for longer. Both ASML and Intel argue that these machines have been designed to help semiconductor manufacturers increase the resolution of their lithographic processes without increasing complexity. In practice, this quality should have a perceptible upward impact on the productivity of the equipment, and, at the same time, a downward impact on the production cost of the chips.
The following slide summarizes what Intel says are the greatest strengths of high-aperture UVE lithography equipment: lithographic processes will be simpler and require fewer intermediate steps; the new mask technology will be aligned with the increase in resolution; It will be possible to monitor the operation of each machine to optimize its performance, etc.
In any case, the most interesting thing is that in theory it is much simpler, more efficient and cheaper to produce highly integrated semiconductors using high-aperture UVE equipment than by resorting to multiple patterning on a less advanced lithography machine. This technique broadly consists of transferring the pattern to the wafer in several passes with the purpose of increasing the resolution of the lithographic process. It may have an upward impact on the cost of chips and a downward impact on production capacity, but it works.
The next slide describes how lithography has improved over the past four decades. The development that this technology has experienced during this time is impressive, but to understand its impact in all its magnitude, we are interested in investigating the equation that acts as the bible of ASML. It is precisely the Rayleigh criterion that I mentioned a few paragraphs above. You can see the equation in the lower left corner of the slide, and it contains all the parameters that determine the performance of the lithography equipment used to manufacture integrated circuits.
At first glance, it may seem like a complicated formula, but in reality, it is not so complicated if we know what each of the terms in the equation represents. I propose that we review them one by one from left to right. The first of them, ‘CD’, comes from the English expression critical dimension, and identifies to what extent it is possible to miniaturize the components that make up an integrated circuit.